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__________________ general description the max187/max189 serial 12-bit analog-to-digital converters (adcs) operate from a single +5v supply and accept a 0v to 5v analog input. both parts feature an 8.5? successive-approximation adc, a fast track/hold (1.5?), an on-chip clock, and a high-speed 3-wire serial interface. the max187/max189 digitize signals at a 75ksps throughput rate. an external clock accesses data from the interface, which communicates without external hardware to most digital signal processors and micro- controllers. the interface is compatible with spi, qspi, and microwire. the max187 has an on-chip buffered reference, and the max189 requires an external reference. both the max187 and max189 save space with 8-pin dip and 16-pin so packages. power consumption is 7.5mw and reduces to only 10? in shutdown. excellent ac characteristics and very low power con- sumption combined with ease of use and small pack- age size make these converters ideal for remote dsp and sensor applications, or for circuits where power consumption and space are crucial. ___________________________ applications portable data logging remote digital signal processing isolated data acquisition high-accuracy process control ________________________________ features ? 12-bit resolution ? 1 2 lsb integral nonlinearity (max187a/max189a) ? internal track/hold, 75khz sampling rate ? single +5v operation ? low power: 2? shutdown current 1.5ma operating current ? internal 4.096v buffered reference (max187) ? 3-wire serial interface, compatible with spi, qspi, and microwire ? small-footprint 8-pin dip and 16-pin so _________________or dering information max187/max189 +5v, low-power, 12-bit serial adcs ________________________________________________________________ maxim integrated products 1 call toll free 1-800-998-8800 for free samples or literature. 19-0196; rev 0; 10/93 part temp. range pin-package error (lsb) max187 acpa 0? to +70? 8 plastic dip 1 2 max187bcpa 0? to +70? 8 plastic dip ? max187ccpa 0? to +70? 8 plastic dip ? max187acwe 0? to +70? 16 wide so 1 2 max187bcwe 0? to +70? 16 wide so ? max187ccwe 0? to +70? 16 wide so ? max187bc/d 0? to +70? dice* ? spi and qspi are trademarks of motorola. microwire is a trademark of national semiconductor. ordering information continued on last page. * dice are specified at t a = +25?, dc parameters only. ** contact factory for availability and processing to mil-std-883. ________________functional diagram gnd 5 ref 4 ain 2 v dd 1 t/h bandgap reference +2.5v (max187 only) 10k av = 1.638 (4.096v) ref- ref+ dac output shift register dout 6 sclk 8 cs 7 shdn 3 control and timing 12-bit sar comparator buffer enable/disable note: pin numbers shown are for 8-pin dips only. max187 max189 top view 1 2 3 4 8 7 6 5 sclk cs dout gnd ref shdn ain v dd dip max187 max189 pin configurations continued on last page. _________________pin configurations evaluation kit manual follows data sheet
max187/max189 +5v, low-power, 12-bit serial adcs 2 _______________________________________________________________________________________ electrical characteristics (v dd = +5v ?%; gnd = 0v; unipolar input mode; 75ksps, f clk = 4.0mhz, external clock (50% duty cycle); max187?nternal reference: v ref = 4.096v, 4.7? capacitor at ref pin, or max189?xternal reference: v ref = 4.096v applied to ref pin, 4.7? capacitor at ref pin; t a = t min to t max ; unless otherwise noted.) parameter symbol conditions min typ max units dc accuracy (note 1) resolution 12 bits max18_a 1 2 relative accuracy (note 2) max18_b ? lsb max18_c ? differential nonlinearity dnl no missing codes over temperature ? lsb offset error max18_a ? 1 2 lsb max18_b/c ? gain error (note 3) max187 ? lsb max189a ? max189b/c ? gain temperature coefficient external reference, 4.096v ?.8 ppm/? dynamic specifications (10khz sine wave input, 0v to 4.096v p-p , 75ksps) signal-to-noise plus distortion ratio sinad 70 db total harmonic distortion (up to the 5th harmonic) thd -80 db spurious-free dynamic range sfdr 80 db small-signal bandwidth rolloff -3db 4.5 mhz full-power bandwidth 0.8 mhz v dd to gnd .............................................................-0.3v to +6v ain to gnd................................................-0.3v to (v dd + 0.3v) ref to gnd ...............................................-0.3v to (v dd + 0.3v) digital inputs to gnd.................................-0.3v to (v dd + 0.3v) digital outputs to gnd..............................-0.3v to (v dd + 0.3v) shdn to gnd.............................................-0.3v to (v dd + 0.3v) ref load current (max187) .........................4.0ma continuous ref short-circuit duration (max187)................................20sec dout current ..................................................................?0ma continuous power dissipation (t a = +70?) 8-pin plastic dip (derate 9.09mw/? above +70?) ..500mw 16-pin wide so (derate 8.70mw/? above +70?) ...478mw 8-pin cerdip (derate 8.00mw/? above +70?) ......440mw operating temperature ranges: max187_c_ _/max189_c_ _.............................0? to +70? max187_e_ _/max189_e_ _ ..........................-40? to +85? max187_mja/max189_mja .......................-55? to +125? storage temperature range............................-60? to +150? lead temperature (soldering, 10sec) ............................+300? absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
parameter symbol conditions min typ max units conversion rate conversion time t conv 5.5 8.5 ? track/hold acquisition time t acq 1.5 ? throughput rate external clock, 4mhz, 13 clocks 75 ksps aperture delay t apr 10 ns aperture jitter <50 ps analog input input voltage range 0 to v ref v input capacitance (note 4) 16 pf internal reference (max187 only, reference buffer enabled) ref output voltage v ref t a = +25? 4.076 4.096 4.116 max187_c 4.060 4.132 t a = t min to t max max187_e 4.050 4.140 v max187_m 4.040 4.150 ref short-circuit current 30 ma max187ac/bc ?0 ?0 ref tempco max187ae/be ?0 ?0 ppm/? max187am/bm ?0 ?0 max187c ?0 load regulation (note 5) 0ma to 0.6ma output load 1 mv external reference at ref (buffer disabled, v ref = 4.096v) input voltage range 2.50 v dd + 50mv v input current 200 350 ? input resistance 12 20 k shutdown ref input current 1.5 10 ? max187/max189 +5v, low-power, 12-bit serial adcs _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = +5v ?%; gnd = 0v; unipolar input mode; 75ksps, f clk = 4.0mhz, external clock (50% duty cycle); max187?nternal reference: v ref = 4.096v, 4.7? capacitor at ref pin, or max189?xternal reference: v ref = 4.096v applied to ref pin, 4.7? capacitor at ref pin; t a = t min to t max ; unless otherwise noted.)
max187/max189 +5v, low-power, 12-bit serial adcs 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = +5v ?%; gnd = 0v; unipolar input mode; 75ksps, f clk = 4.0mhz, external clock (50% duty cycle); max187?nternal reference: v ref = 4.096v, 4.7? capacitor at ref pin, or max189?xternal reference: v ref = 4.096v applied to ref pin, 4.7? capacitor at ref pin; t a = t min to t max ; unless otherwise noted.) parameter symbol conditions min typ max units digital inputs (sclk, cs , shdn ) sclk, cs input high voltage v inh 2.4 v sclk, cs input low voltage v inl 0.8 v sclk, cs input hysteresis v hyst 0.15 v sclk, cs input leakage i in v in = 0v or v dd ? ? sclk, cs input capacitance c in (note 4) 15 pf shdn input high voltage v insh v dd - 0.5 v shdn input low voltage v insl 0.5 v shdn input current i ins shdn = v dd or 0v ?.0 ? shdn input mid voltage v im 1.5 v dd -1.5 v shdn voltage, floating v flt shdn = open 2.75 v shdn maximum allowed shdn = open -100 100 na leakage, mid input digital output (dout) output voltage low v ol i sink = 5ma 0.4 v i sink = 16ma 0.3 output voltage high v oh i source = 1ma 4 v three-state leakage current i l cs = 5v ?0 ? three-state output c out cs = 5v (note 4) 15 pf capacitance power requirements supply voltage v dd 4.75 5.25 v supply current operating mode max187 1.5 2.5 ma i dd max189 1.0 2.0 power-down mode 2 10 a v dd = +5v, ?%; external reference, 4.096v; power-supply rejection psr full-scale input (note 6) ?.06 ?.5 mv
max187/max189 +5v, low-power, 12-bit serial adcs _______________________________________________________________________________________ 5 timing characteristics (v dd = +5.0v ?%, t a = t min to t max , unless otherwise noted.) parameter symbol conditions min typ max units track/hold acquisition time t acq cs = high (note 7) 1.5 ? sclk fall to output data valid t do c load = 100pf max18_ _c/e 20 150 ns max18_ _m 20 200 cs fall to output enable t dv c load = 100pf 100 ns cs rise to output disable t tr c load = 100pf 100 ns sclk clock frequency f sclk 5 mhz sclk pulse width high t ch 100 ns sclk pulse width low t cl 100 ns sclk low to cs fall t cso 50 ns setup time cs pulse width t cs 500 ns note 1: tested at v dd = +5v. note 2: relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has been calibrated. note 3: max187?nternal reference, offset nulled; max189?xternal +4.096v reference, offset nulled. excludes reference errors. note 4: guaranteed by design. not subject to production testing. note 5: external load should not change during conversion for specified adc accuracy. note 6: dc test, measured at 4.75v and 5.25v only. note 7: to guarantee acquisition time, t acq is the maximum time the device takes to acquire the signal, and is also the minimum time needed for the signal to be acquired.
max187/max189 +5v, low-power, 12-bit serial adcs 6 _______________________________________________________________________________________ 0.12 0.10 0.08 0.06 0.04 0.02 0 -60 -20 20 60 100 140 temperature (?) power-supply rejection (mv) power-supply rejection vs. temperature 0.14 0.16 4.090 4.087 4.084 4.081 -60 -20 20 60 140 temperature (?) internal reference voltage (v) v ref vs. temperature 100 4.089 4.088 4.086 4.085 4.083 4.082 4.080 1.8 1.4 1.0 0.6 0.2 -60 -20 20 60 100 140 temperature (?) supply current (ma) max187 max189 supply current vs. temperature 2.2 ________________________________________________t ypical operating characteristics 5 4 3 2 1 0 -60 -20 20 60 100 140 temperature (?) shutdown supply current ( m a) shutdown supply current vs. temperature 6 7
max187/max189 +5v, low-power, 12-bit serial adcs _______________________________________________________________________________________ 7 pin dip wide so name function 11v dd supply voltage, +5v ?% 2 3 ain sampling analog input, 0v to v ref range 36 shdn three-level shutdown input. pulling shdn low shuts the max187/max189 down to 10? (max) supply current. both max187 and max189 are fully opera- tional with either shdn high or floating. for the max187, pulling shdn high enables the internal reference, and letting shdn float disables the internal reference and allows for the use of an external reference. 4 8 ref reference voltage?ets analog voltage range and functions as a 4.096v output for the max187 with enabled internal reference. ref also serves as a +2.5v to v dd input for a precision reference for both max187 (disabled internal reference) and max189. bypass with 4.7? if internal reference is used, and with 0.1? if an external reference is applied. 5 gnd analog and digital ground 10 agnd analog ground 11 dgnd digital ground 6 12 dout serial data output. data changes state at sclk? falling edge. 715 cs active-low chip select initiates conversions on the falling edge. when cs is high, dout is high impedance. 8 16 sclk serial clock input. clocks data out with rates up to 5mhz. 2,4,5,7,9,13,14 n.c. not internally connected. connect to agnd for best noise performance. _______________________________________________________________________ pin description _______________detailed description converter operation the max187/max189 use input track/hold (t/h) and successive approximation register (sar) circuitry to convert an analog input signal to a digital 12-bit output. no external hold capacitor is needed for the t/h. figures 3a and 3b show the max187/max189 in their simplest configuration. the max187/max189 convert input signals in the 0v to v ref range in 10?, including t/h acquisition time. the max187? internal reference is trimmed to 4.096v, while the max189 requires an external reference. both devices accept external refer- ence voltages from +2.5v to v dd . the serial interface requires only three digital lines, sclk, cs, and dout, and provides easy interface to microprocessors ( m ps). both converters have two modes: normal and shut- down. pulling shdn low shuts the device down and reduces supply current to below 10?, while pulling shdn high or leaving it floating puts the device into the operational mode. a conversion is initiated by cs falling. the conversion result is available at dout in unipolar serial format. a high bit, signaling the end of conversion (eoc), followed by the data bits (msb first), make up the serial data stream. the max187 operates in one of two states: (1) internal reference and (2) external reference. select internal reference operation by forcing shdn high, and external reference operation by floating shdn . analog input figure 4 illustrates the sampling architecture of the adc? analog comparator. the full-scale input voltage depends on the voltage at ref. reference zero full scale scale internal reference 0v +4.096v (max187 only) external reference 0v v ref for specified accuracy, the external reference voltage range spans from +2.5v to v dd .
max187/max189 +5v, low-power, 12-bit serial adcs 8 _______________________________________________________________________________________ dout dout 3k dgnd c load = 100pf c load = 100pf 3k dgnd +5v b. high-z to v ol and v oh to v ol a. high-z to v oh and v ol to v oh dout dout 3k dgnd c load = 100pf c load = 100pf 3k dgnd +5v b. v ol to high-z a. v oh to high-z figure 1. load circuits for dout enable time figure 2. load circuits for dout disable time
track/hold in track mode, the analog signal is acquired and stored in the internal hold capacitor. in hold mode, the t/h switch opens and maintains a constant input to the adc? sar section. during acquisition, the analog input ain charges capacitor c hold . bringing cs low ends the acquisition interval. at this instant, the t/h switches the input side of c hold to gnd. the retained charge on c hold rep- resents a sample of the input, unbalancing the node zero at the comparator? input. in hold mode, the capacitive dac adjusts during the remainder of the conversion cycle to restore node zero to 0v within the limits of a 12-bit resolution. this action is equivalent to transferring a charge from c hold to the binary-weighted capacitive dac, which in turn forms a digital representation of the analog input signal. at the conversion? end, the input side of c hold switches back to ain, and c hold charges to the input signal again. the time required for the t/h to acquire an input signal is a function of how quickly its input capacitance is charged. if the input signal? source impedance is high, the acquisition time lengthens and more time must be allowed between conversions. acquisition time is calculated by: t acq = 9 (r s + r in ) 16pf, where r in = 5k , r s = the source impedance of the input signal, and t acq is never less than 1.5?. source impedances below 5k do not significantly affect the ac performance of the adc. max187/max189 +5v, low-power, 12-bit serial adcs _______________________________________________________________________________________ 9 ain track input hold c package gnd track hold 5k r in c hold 16pf -+ c switch comparator zero ref 12-bit capacitive dac at the sampling instant, the input switches from ain to gnd. on off shutdown input analog input 0v to +5v +5v 1 2 3 4 v dd ain shdn ref 8 7 6 5 sclk cs dout gnd serial interface 0.1 m f 4.7 m f 0.1 m f reference input max189 on off shutdown input analog input 0v to +5v +5v 1 2 3 4 v dd ain shdn ref 8 7 6 5 sclk cs dout gnd serial interface 4.7 m f 4.7 m f 0.1 m f max187 figure 3a. max187 operational diagram figure 3b. max189 operational diagram figure 4. equivalent input circuit
max187/max189 +5v, low-power, 12-bit serial adcs 10 ______________________________________________________________________________________ complete conversion sequence t wake powered up powered down powered up conversion 0 conversion 1 dout cs shdn input bandwidth the adcs?input tracking circuitry has a 4.5mhz small- signal bandwidth, and an 8v/? slew rate. it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the adc's sampling rate by using undersampling techniques. to avoid aliasing of unwanted high-frequency signals into the frequency band of interest, an anti-alias filter is rec- ommended. see the max274/max275 continuous-time filters data sheet. input protection internal protection diodes that clamp the analog input allow the input to swing from gnd - 0.3v to v dd + 0.3v without damage. however, for accurate conversions near full scale, the input must not exceed v dd by more than 50mv, or be lower than gnd by 50mv. if the analog input exceeds the supplies by more than 50mv beyond the supplies, limit the input current to 2ma, since larger currents degrade conversion accuracy. driving the analog input the input lines to ain and gnd should be kept as short as possible to minimize noise pickup. shield longer leads. also see the input protection section . because the max187/max189 incorporate a t/h, the drive requirements of the op amp driving ain are less stringent than those for a successive-approximation adc without a t/h. the typical input capacitance is 16pf. the amplifier bandwidth should be sufficient to handle the frequency of the input signal. the max400 and op07 work well at lower frequencies. for higher- frequency operation, the max427 and op27 are practi- cal choices. the allowed input frequency range is limit- ed by the 75ksps sample rate of the max187/max189. therefore, the maximum sinusoidal input frequency allowed is 37.5khz. higher-frequency signals cause aliasing problems unless undersampling techniques are used. reference the max187 can be used with an internal or external ref- erence, while the max189 requires an external reference. internal reference the max187 has an on-chip reference with a buffered temperature-compensated bandgap diode, laser- trimmed to +4.096v ?.5%. its output is connected to ref and also drives the internal dac. the output can be used as a reference voltage source for other com- ponents and can source up to 0.6ma. decouple ref with a 4.7? capacitor. the internal reference is enabled by pulling the shdn pin high. letting shdn float disables the internal reference, which allows the use of an external reference, as described in the external reference section. external reference the max189 operates with an external reference at the ref pin. to use the max187 with an external reference, disable the internal reference by letting shdn float. stay within the voltage range +2.5v to v dd to achieve speci- fied accuracy. the minimum input impedance is 12k for dc currents. during conversion, the external refer- ence must be able to deliver up to 350? dc load cur- rent and have an output impedance of 10 or less. the recommended minimum value for the bypass capacitor is 0.1?. if the reference has higher output impedance or is noisy, bypass it close to the ref pin with a 4.7? capacitor. figure 5. max187/max189 shutdown sequence
____________________serial interface initialization after power-up and starting a conversion when power is first applied, it takes the fully dis- charged 4.7? reference bypass capacitor up to 20ms to provide adequate charge for specified accuracy. with shdn not pulled low, the max187/max189 are now ready to convert. to start a conversion, pull cs low. at cs ? falling edge, the t/h enters its hold mode and a conversion is initiat- ed. after an internally timed 8.5? conversion period, the end of conversion is signaled by dout pulling high. data can then be shifted out serially with the external clock. using shdn to reduce supply current power consumption can be reduced significantly by shutting down the max187/max189 between conver- sions. this is shown in figure 6, a plot of average sup- ply current vs. conversion rate. because the max189 uses an external reference voltage (assumed to be pre- sent continuously), it "wakes up" from shutdown more quickly, and therefore provides lower average supply currents. the wakeup-time, t wake, is the time from shdn deasserted to the time when a conversion may be initiated. for the max187, this time is 2s. for the max189, this time depends on the time in shutdown (see figure 7) because the external 4.7? reference bypass capacitor loses charge slowly during shutdown (see the specifications for shutdown, ref input current = 10? max). external clock the actual conversion does not require the external clock. this frees the ? from the burden of running the sar conversion clock, and allows the conversion result to be read back at the ?? convenience at any clock rate from 0mhz to 5mhz. the clock duty cycle is unre- stricted if each clock phase is at least 100ns. do not run the clock while a conversion is in progress. timing and control conversion-start and data-read operations are con- trolled by the cs and sclk digital inputs. the timing diagrams of figures 8 and 9 outline the operation of the serial interface. a cs falling edge initiates a conversion sequence: the t/h stage holds input voltage, the adc begins to con- vert, and dout changes from high impedance to logic low. sclk must be kept inactive during the conversion. an internal register stores the data when the conversion is in progress. end of conversion (eoc) is signaled by dout going high. dout? rising edge can be used as a framing signal. sclk shifts the data out of this register any time after the conversion is complete. dout transitions on sclk? falling edge. the next falling clock edge pro- duces the msb of the conversion at dout, followed by the remaining bits. since there are 12 data bits and one leading high bit, at least 13 falling clock edges are needed to shift out these bits. extra clock pulses occur- ring after the conversion result has been clocked out, and prior to a rising edge of cs , produce trailing 0s at dout and have no effect on converter operation. +5v, low-power, 12-bit serial adcs ______________________________________________________________________________________ 11 10000 1000 100 10 1 0.1 1 10 100 1000 10000 conversions per second supply current ( m a) 100000 max187 max189* *ref connected to v dd 3.0 2.5 2.0 1.5 1.0 0.5 0 0.0001 0.001 0.01 0.1 1 10 time in shutdown (sec) t wake (ms) max187/max189 figure 6. average supply current vs. conversion rate figure 7. t wake vs. time in shutdown (max187 only)
max187/max189 +5v, low-power, 12-bit serial adcs 12 ______________________________________________________________________________________ cs sclk dout interface idle conversion in progress eoc eoc a/d state track conversion 0 0 m s 8.5 m s (t conv ) trailing zeros idle 0 m s 0.5 m s (t cs ) total = 12.25 m s conv. 1 clock output data track 12 0.250 m s = 3.25 m s b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 14 8 12 minimum cycle time ? ? ? ? cs sclk dout internal t/h (track) t cs0 t conv t dv t apr (hold) (track) b2 b1 b0 t ch t do t cl t tr t cs figure 8. max187/max189 interface timing sequence figure 9. max187/max189 detailed serial-interface timing
minimum cycle time is accomplished by using dout? rising edge as the eoc signal. clock out the data with 13 clock cycles at full speed. raise cs after the conver- sion? lsb has been read. after the specified minimum time, t acq , cs can be pulled low again to initiate the next conversion. output coding and transfer function the data output from the max187/max189 is binary, and figure 10 depicts the nominal transfer function. code transitions occur halfway between successive integer lsb values. if v ref = +4.096v, then 1 lsb = 1.00mv or 4.096v/4096. _____________dynamic performance high-speed sampling capability and a 75ksps through- put make the max187/max189 ideal for wideband sig- nal processing. to support these and other related applications, fast fourier transform (fft) test tech- niques are used to guarantee the adc? dynamic fre- quency response, distortion, and noise at the rated throughput. specifically, this involves applying a low- distortion sine wave to the adc input and recording the digital conversion results for a specified time. the data is then analyzed using an fft algorithm that deter- mines its spectral content. conversion errors are then seen as spectral elements outside of the fundamental input frequency. adcs have traditionally been evaluat- ed by specifications such as zero and full-scale error, integral nonlinearity (inl), and differential nonlinearity (dnl). such parameters are widely accepted for speci- fying performance with dc and slowly varying signals, but are less useful in signal-processing applications, where the adc? impact on the system transfer function is the main concern. the significance of various dc errors does not translate well to the dynamic case, so different tests are required. signal-to-noise ratio and effective number of bits signal-to-noise plus distortion (sinad) is the ratio of the fundamental input frequency? rms amplitude to the rms amplitude of all other adc output signals. the input bandwidth is limited to frequencies above dc and below one-half the adc sample (conversion) rate. the theoretical minimum adc noise is caused by quan- tization error and is a direct result of the adc? resolu- tion: sinad = (6.02n + 1.76)db, where n is the number of bits of resolution. an ideal 12-bit adc can, therefore, do no better than 74db. an fft plot of the output shows the output level in various spectral bands. figure 11 shows the result of sampling a pure 10khz sine wave at a 75ksps rate with the max187/max189. max187/max189 +5v, low-power, 12-bit serial adcs ______________________________________________________________________________________ 13 11 ? 111 11 ? 110 11 ? 101 00 ? 011 00 ? 010 00 ? 001 00 ? 000 012 fs output code fs - 3/2lsb input voltage (lsbs) fs = +4.096v 1lsb = fs 4096 full-scale transition 3 amplitude (db) 20 0 -20 -40 -60 -80 -100 -120 -140 0 18.75 37.5 f s = 75ksps f t = 10khz t a = +25? frequency (khz) figure 11. max187/max189 fft plot figure 10. max187/max189 unipolar transfer function, 4.096v = full scale
max187/max189 +5v, low-power, 12-bit serial adcs 14 ______________________________________________________________________________________ 11.8 11.6 11.4 11.2 11.0 10.8 10.6 10.4 10.2 1 10 100 1000 (undersampled) effective bits input frequency (khz) 12.0 12.2 max187 max189 cs sclk dout i/o sck miso +5v ss a. spi max187 max189 cs sclk dout cs sck miso +5v ss b. qspi max187 max189 cs sclk dout i/o sk si c. microwire figure 13. common serial-interface connections to the max187/max189 figure 12. effective bits vs. input frequency the effective resolution (effective number of bits) the adc provides can be determined by transposing the above equation and substituting in the measured sinad: n = (sinad - 1.76)/6.02. figure 12 shows the effective number of bits as a function of the input fre- quency for the max187/max189. total harmonic distortion if a pure sine wave is sampled by an adc at greater than the nyquist frequency, the nonlinearities in the adc? transfer function create harmonics of the input frequency present in the sampled output data. total harmonic distortion (thd) is the ratio of the rms sum of all the harmonics (in the frequency band above dc and below one-half the sample rate, but not includ- ing the dc component) to the rms amplitude of the fundamental frequency. this is expressed as follows: thd = 20log v 2 2 + v 3 2 + v 4 2 + ?v n 2 v 1 where v 1 is the fundamental rms amplitude, and v 2 through v n are the amplitudes of the 2nd through nth harmonics. the thd specification in the electrical characteristics includes the 2nd through 5th harmonics.
____________ applications information connection to standard interfaces the max187/max189 serial interface is fully compatible with spi, qspi, and microwire standard serial interfaces. if a serial interface is available, set the cpu? serial interface in master mode so the cpu generates the ser- ial clock. choose a clock frequency up to 2.5mhz. 1. use a general-purpose i/o line on the cpu to pull cs low. keep sclk low. 2. wait the for the maximum conversion time specified before activating sclk. alternatively, look for a dout rising edge to determine the end of conversion. 3. activate sclk for a minimum of 13 clock cycles. the first falling clock edge will produce the msb of the dout conversion. dout output data transitions on sclk? falling edge and is available in msb-first for- mat. observe the sclk to dout valid timing charac- teristic. data can be clocked into the ? on sclk? rising edge. 4. pull cs high at or after the 13th falling clock edge. if cs remains low, trailing zeros are clocked out after the lsb. 5. with cs = high, wait the minimum specified time, t cs , before launching a new conversion by pulling cs low. if a conversion is aborted by pulling cs high before the conversions end, wait for the minimum acquisition time, t acq , before starting a new conversion. data can be output in 1-byte chunks or continuously, as shown in figure 8. the bytes will contain the result of the conversion padded with one leading 1, and trailing 0s if sclk is still active with cs kept low. max187/max189 +5v, low-power, 12-bit serial adcs ______________________________________________________________________________________ 15 msb d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 lsb hi-z t conv dout cs sclk hi-z 1st byte read 2nd byte read eoc msb d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 lsb hi-z t conv dout cs sclk hi-z eoc figure 14. spi/microwire serial interface timing (cpol = cpha = 0) figure 15. qspi serial interface timing (cpol = cpha = 0)
max187/max189 spi and microwire when using spi or qspi, set cpol = 0 and cpha = 0. conversion begins with a cs falling edge. dout goes low, indicating a conversion in progress. wait until dout goes high or the maximum specified 8.5? con- version time. two consecutive 1-byte reads are required to get the full 12 bits from the adc. dout out- put data transitions on sclk? falling edge and is clocked into the ? on sclk? rising edge. the first byte contains a leading 1 and 7 bits of conver- sion result. the second byte contains the remaining 5 bits and 3 trailing 0s. see figure 13 for connections and figure 14 for timing. qspi set cpol = cpha = 0. unlike spi, which requires two 1-byte reads to acquire the 12 bits of data from the adc, qspi allows the minimum number of clock cycles necessary to clock in the data. the max187/max189 require 13 clock cycles from the ? to clock out the 12 bits of data with no trailing 0s (figure 15). the maxi- mum clock frequency to ensure compatibility with qspi is 2.77mhz. opto-isolated interface, serial-to-parallel conversion many industrial applications require electrical isolation to separate the control electronics from hazardous electrical conditions, provide noise immunity, or pre- vent excessive current flow where ground disparities exist between the adc and the rest of the system. isolation amplifiers typically used to accomplish these tasks are expensive. in cases where the signal is even- tually converted to a digital form, it is cost effective to isolate the input using opto-couplers in a serial link. the max187 is ideal in this application because it includes both t/h amplifier and voltage reference, operates from a single supply, and consumes very little power (figure 16). +5v, low-power, 12-bit serial adcs 16 ______________________________________________________________________________________ max187 analog input signal ground 4.7 m f5 4 2 1 6 8 7 3 10 m f 0.1 m f gnd ref ain v dd dout sclk cs shdn +5v 3k 3k 470 w 8 7 6 5 1 2 3 4 200 w 200 w +5v 8 7 6 5 1 2 3 4 1 2 3 4 8 7 6 5 +5v on this side of barrier must be isolated power 6n136 6n136 6n136 74hc04 74hc04 8.2k +5v 14 11 12 10 7 6 5 4 3 2 1 15 16 d11 (msb) d10 d9 d8 +5v 0.1 m f cs/start sclk/input clock ser sck rck sclr qh qg qf qe qd qc qb qa 13 8 9 7 6 5 4 3 2 1 15 16 +5v 0.1 m f 13 8 14 11 12 10 74hc595 74hc595 ser sck rck sclr qh qg qf qe qd qc qb qa qh d0(lsb) d1 d2 d3 d4 d5 d6 d7 figure 16. 12-bit isolated adc
max187/max189 +5v, low-power, 12-bit serial adcs ______________________________________________________________________________________ 17 supplies +5v gnd dgnd +5v digital circuitry dgnd agnd v dd max187 max189 *optional r* = 10 w 4.7 m f 0.01 m f the adc results are transmitted across a 1500v isola- tion barrier provided by three 6n136 opto-isolators. isolated power must be supplied to the converter and the isolated side of the opto-couplers. 74hc595 three- state shift registers are used to construct a 12-bit paral- lel data output. the timing sequence is identical to the timing shown in figure 8. conversion speed is limited by the delay through the opto-isolators. with a 140khz clock, conversion time is 100?. the universal 12-bit parallel data output can also be used without the isolation stage when a parallel inter- face is required. clock frequencies up to 2.9mhz are possible without violating the 20ns shift-register setup time. delay or invert the clock signal to the shift regis- ters beyond 2.9mhz. layout, grounding, bypassing for best performance, use printed circuit boards. wire- wrap boards are not recommended. board layout should ensure that digital and analog signal lines are separated from each other. do not run analog and digi- tal (especially clock) lines parallel to one another, or digital lines underneath the adc package. figure 17 shows the recommended system ground connections. a single-point analog ground (?tar ground point) should be established at gnd, separate from the logic ground. all other analog grounds should be connected to this ground. the 16-pin versions also have a dedicated dgnd pin available. connect dgnd to this star ground point for further noise reduction. no other digital system ground should be connected to this single-point analog ground. the ground return to the power supply for this ground should be low imped- ance and as short as possible for noise-free operation. high-frequency noise in the v dd power supply may affect the adc? high-speed comparator. bypass this supply to the single-point analog ground with 0.01? and 4.7? bypass capacitors. minimize capacitor lead lengths for best supply-noise rejection. if the +5v power supply is very noisy, a 10 resistor can be con- nected as a lowpass filter to attenuate supply noise (figure 17). figure 17. power-supply grounding condition
max187/max189 +5v, low-power, 12-bit serial adcs 18 ______________________________________________________________________________________ __ordering information (continued) part temp. range pin-package error (lsb) max187aepa -40? to +85? 8 plastic dip 1 2 max187bepa -40? to +85? 8 plastic dip ? max187cepa -40? to +85? 8 plastic dip ? max187aewe -40? to +85? 16 wide so 1 2 max187bewe -40? to +85? 16 wide so ? max187cewe -40? to +85? 16 wide so ? max187amja -55? to +125? 8 cerdip** 1 2 max187bmja -55? to +125? 8 cerdip** ? max189 acpa 0? to +70? 8 plastic dip 1 2 max189bcpa 0? to +70? 8 plastic dip ? max189ccpa 0? to +70? 8 plastic dip ? max189acwe 0? to +70? 16 wide so 1 2 max189bcwe 0? to +70? 16 wide so ? max189ccwe 0? to +70? 16 wide so ? max189bc/d 0? to +70? dice* ? max189aepa -40? to +85? 8 plastic dip 1 2 max189bepa -40? to +85? 8 plastic dip ? max189cepa -40? to +85? 8 plastic dip ? max189aewe -40? to +85? 16 wide so 1 2 max189bewe -40? to +85? 16 wide so ? max189cewe -40? to +85? 16 wide so ? max189amja -55? to +125? 8 cerdip** 1 2 max189bmja -55? to +125? 8 cerdip** ? * dice are specified at t a = +25?, dc parameters only. **contact factory for availability and processing to mil-std-883. ____pin configurations (continued) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 sclk cs n.c. n.c. n.c. ain n.c. v dd max187 max189 dout dgnd agnd n.c. ref n.c. shdn n.c. wide so
max187/max189 +5v, low-power, 12-bit serial adcs ______________________________________________________________________________________ 19 ___________________chip topography dgnd ain agnd 0.151" (3.84mm) 0.117" (2.97mm) ref agnd dout v dd sclk shdn cs transistor count: 2278; substrate connected to v dd . max187/max189
maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 20 __________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 (408) 737-7600 1993 maxim integrated products printed usa is a registered trademark of maxim integrated products. max187/max189 +5v, low-power, 12-bit serial adcs ________________________________________________________________ package information dim a a1 b c e e h l min 0.093 0.004 0.014 0.009 0.291 0.394 0.016 max 0.104 0.012 0.019 0.013 0.299 0.419 0.050 min 2.35 0.10 0.35 0.23 7.40 10.00 0.40 max 2.65 0.30 0.49 0.32 7.60 10.65 1.27 inches millimeters 21-0042a w package small outline dim d d d d d min 0.398 0.447 0.496 0.598 0.697 max 0.413 0.463 0.512 0.614 0.713 min 10.10 11.35 12.60 15.20 17.70 max 10.50 11.75 13.00 15.60 18.10 inches millimeters pins 16 18 20 24 28 1.27 0.050 l h e d e a a1 c 0? 8 0.101mm 0.005in. b dim a a1 a2 a3 b b1 c d1 e e1 e ea eb l min ? 0.015 0.125 0.055 0.016 0.045 0.008 0.050 0.600 0.525 0.100 0.600 ? 0.120 max 0.200 ? 0.175 0.080 0.020 0.065 0.012 0.090 0.625 0.575 ? ? 0.700 0.150 min ? 0.38 3.18 1.40 0.41 1.14 0.20 1.27 15.24 13.34 2.54 15.24 ? 3.05 max 5.08 ? 4.45 2.03 0.51 1.65 0.30 2.29 15.88 14.61 ? ? 17.78 3.81 inches millimeters p package plastic dual-in-line dim d d d min 1.230 1.430 2.025 max 1.270 1.470 2.075 min 31.24 36.32 51.44 max 32.26 37.34 52.71 inches millimeters pins 24 28 40 c a a2 e1 d e ea eb a3 b1 0?15 b a1 l d1 e

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